1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particular, to a semiconductor memory device using fuses.
2. Description of the Related Art
Semiconductor integrated circuit have multiple component circuits of the same pattern. Semiconductor integrated circuits also have redundancy circuits to replace failed component circuits.
Semiconductor memory devices have a large number of memory cells integrated in a single chip. When even one memory cells fails, its memory chip may not function normally and would need to be discarded. Since there are many memory cells in a single chip, it is common for one or more of them to be defective. Thus, in order to retain those chips having failed cells to increase yield, most semiconductor memory devices have fuse circuits and redundancy cell arrays.
Semiconductor memory devices have fuse circuits for setting initial values.
A conventional fuse circuit uses a laser fuse that resembles metal wiring, and programs the fuse by selectively cutting the metal wiring using a laser beam. That is, depending on whether the fuse is blown, the fuse circuit provides desired information to the semiconductor integrated circuit.
However, the laser fuse circuit requires continuous equipment investment due to the reduction in pitch between lines depending on the level of integration in the semiconductor integrated circuit. Furthermore, laser fuse circuits require a lot of time for fuse programming. Furthermore, the fuse array occupies a relatively large area, and the laser fuse circuit can program fuses at the wafer level, but cannot program fuses at the package level.
Recently, E-fuses have begun to replace laser fuses. E-fuses have received attention because they are capable of overcoming many of the disadvantages of laser fuses. An E-fuse resembles a transistor, and ruptures its gate dielectric layer by applying a high electric field to a gate for it to be programmed.
An E-fuse circuit may be implemented in various forms. Array E-fuse circuits, which as fuse cells arranged in an array (hereafter, referred to as a fuse array), are widely used. During initialization or power-up operations of a semiconductor integrated circuit, data programmed in the fuse array is read and latched for later use. The operation of latching the programmed data of the fuse array may be referred to as a boot-up operation. The boot-up operation shortens the time for accessing the data of the fuse array.
As the integration of semiconductor integrated circuits increases, the amount of data stored in the fuse array also increases. Thus, both the area occupied by the fuse array and the area occupied by latches has increased significantly.
Latches for latching data of the fuse array is generally accomplished using SRAM, which maintains the logic level of data stored therein using CMOS transistors. However, as the integration increases to store more data, the soft error rate (SER) also increases. The SER is the probability of soft errors, where SRAM data is lost, due to neutrons.